-- 
-- Blokje meten testbench
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fc_meten_tb is
end fc_meten_tb;

architecture testbench of fc_meten_tb is
	component fc_meten is
		port( 
			reed : in std_logic := '1';
			clk	: in std_logic;
			rst : in std_logic;
			deltat : out std_logic_vector(63 downto 0);
			deltat_strobe : buffer std_logic;
			time_out : buffer std_logic
		);
	end component fc_meten;
	
	signal reed : std_logic;
	signal clk : std_logic;
	signal rst : std_logic;
	
	signal deltat : std_logic_vector(63 downto 0);
	signal deltat_strobe : std_logic;
	signal time_out : std_logic;
	
begin
	clockgen: process 
	begin
		clk <= '1';
		wait for 50 us;
		clk <= '0';
		wait for 50 us;
	end process;
	
	datagen: process
	begin
		rst <= '1';
		wait for 200 us;
		rst <= '0';
		
		wait for 200 us;
		reed <= '1';
		wait for 20 ms;
		reed <= '0';
		wait for 300 us;
		reed <= '1';
		wait for 400 us;
		reed <= '0';
		wait for 300 ms;
		
		reed <= '1';
		wait for 200 us;
		reed <= '0';
		wait for 400 us;
		reed <= '1';
		wait for 500 ms;
		reed <= '0';
		wait for 300 us;
		reed <= '1';
		wait for 400 us;
		reed <= '0';
		wait for 300 ms;
		reed <= '1';
		wait for 200 us;
		reed <= '0';
		wait for 300 us;
		reed <= '1';
		wait for 10 ms;
		
		wait;
	end process;
	
	meten: fc_meten port map(
		reed => reed,
		clk => clk,
		rst => rst,
		
		deltat => deltat,
		deltat_strobe => deltat_strobe,
		time_out => time_out
	);
end architecture;